OBS! Ansökningsperioden för denna annonsen har
passerat.
Arbetsbeskrivning
10 Years of Experience in VLSI Design, Development and Implementation of ASIC, FPGA based Applications primarily using Verilog, VHDL.
Proficient in HDLs (Verilog/VHDL).
Experience in RTL Design, synthesis design techniques.
Experience in Block level verification, Functional verification using Verilog.
Experience in Test plan development, Execution, Code coverage.
Knowledge on HVL System Verilog and verification methodology UVM, OVM, VMM.