ASIC Verifikationsingenjör

Om du är intresserat att jobba som konsult samt söker efter ett företag med stort kontaktnätverk inom branschen samt där du själv kan få ut det mesta av av frukten för dina ansträngningar då är RK Lunds Entreprenad AB ett företag för dig. Iom att våra oveheadkostnader är minimala så kan vi erbjuda er en mycket hög andel av kundarvodet som lön.
Vi söker i första hand dig som vill jobba som anställd men även arbete som underkonsult är ett alternativ.


Job description:
The job involves subsystem verification within company´s digital ASIC projects.
The goal of the subsystem verification is to verify that the functional requirements of our subsystems are fulfilled before tape-out of the ASIC.


The work includes:
-Verification planning
-Verification specification
-Verification environment (creation/adaptation/maintenance).
-Test case creation
-Atomization
-Test case execution
-Writing bug reports


The consultant will be part of a team which is responsible for ASIC Level Verification, creation of test benches and DFT Verification.


A successful candidate is an experienced verification engineer with 5 or more years of experience as well good understanding and knowledge about HW designs. Knowledge in Mentor Tool flow, UVM methodology, MIPI Standard Ifs and fundamental 3GPP knowledge is also appreciated. Personal profile should include a positive attitude, a desire to assist fellow engineers, structured way of working, care with details and a natural talent in communicating with others and a passion to reach a common goal. Written and spoken English skills are of course required and the person must be thorough and able to work with many different kinds of personalities. The work will be carried out in close cooperation with subsystem integrators.

The job will require in depth analysis of new functionality, analysis of how to verify the new functionality, analysis of how to implement test code and test cases in the test system and a mindset to find defects.


Required competence
? Excellent knowledge in UVM/OVM for HW verification.
? Excellent System Verilog skills.
? Experience in system level verification.
? Knowledge of hardware design (VHDL/Verilog).
? Experienced in using Mentor tools.
? Knowledge of verification methodology.

? Education level: Master of Science or similar.



Desired competence
? Good programming skills (C).
? Experience from Python or similar scripting languages.
? Experience of SW design for an embedded environment.
? Experience in System Level Verification.
? Experienced in WCDMA, GSM and/or LTE systems.


Overtime and travelling may be required.



Assignment duration

Start date: 2014-03-03.
End date: 2014-09-30.

Possibility for further extension.