Senior ASIC Verification Engineer

Aurenav is looking to fill 4 Senior ASIC Verification Engineering positions at our Stockholm, Sweden office

Qualifications and requirements:

Job description
Developing advanced systems with high data rates.
You will working with among the most advanced and complex ASIC's in the world in 28 nm.
You will be working in a team of several ASIC developers.

Competence/Experience - Must have
Long Experience of ASIC verification with Specman (e language, tools and methodology and building eVC's)
Experience of developing eVC's and test benches, preferably from scratch
Long Experience from block level verification, functional verification, test coverage strategies
Experience of constrained random verification, functional coverage and building verification testbenches with Specman
Experience of working with complex digital ASIC verification with several DSP's, CPU's and high speed links
Experience from formal verification, e.g. using assertions and constraints
Experience of design in VHDL
Fluent in English (verbal and writing)

Competence/Experience - Nice to have
Experience of working with SystemVerilog UVM (pref) or OVM
Experience of developing oVC's/uVC's and test benches, preferably from scratch
Long experience from ASIC top level/system/SoC level verification and test coverage strategies
Long Experience from top level verification with Specman
Experience from C or C++ programming for top level verification
Experience of SystemC
Experience from top level verification using TLM (transaction level model)

Personality
Self-motivated and driven, take initiative, open, see big picture, like challenges
Social, team player

Assignment info
Location: Stockholm onsite
Assignment start: ASAP

Full Time Work