Senior ASIC verification SystemVerilog

Job description
- Wou will partly be working as a consultant.
- You will be working with advanced verification of complex and large ASIC designs.
- You will working with among the most advanced and complex ASIC's in the world in 28 nm.
- You will be working in a team of several ASIC developers.

Competence/Experience - Must have
- Long Experience of working with complex ASIC verification with several million gates, several DSP's, CPU's and high speed links
- Several years experience of working with SystemVerilog UVM (pref) or OVM
- Experience from top level and block level verification
- Experience from functional verification, test coverage strategies
- Experience from high speed links verification or high speed memory or memory controller verification
- Experience of developing oVC's/uVC's from scratch
- Experience of developing test benches using OVC for SystemVerilog from scratch
- Experience from Constrained random verification
- Experience from functional coverage
- Fluent in English (verbal and writing)

Competence/Experience - Nice to have
- Experience from digital filter verification
- Experience of code verification in C or C++
- Experience of design i VHDL
- Experience from formal verification, using assertions and constraints
- Experience from top level verification
- Experience of SystemC and TLM
- Experience of Specman (e language, tools and methodology and building eVC's)
- Fluent in Swedish (verbal and writing)

Personality
- Self-motivated and driven, take initiative, open, see big picture, like challenges
- Social, team player

Assignment info
- Location: Stockholm onsite
- Assignment start: ASAP
- Assignment duration: initially 6 months, with high possibility for long term extension, more than 1-2 years