Senior Digital IP Developer

One of our customers is looking for a Senior Digital IP Developer. This is a consulting assignment.
 
Role Description
The project scope is to develop new radio technology for 5G.
You will work with RTL design in System Verilog.
The work will be carried out in close cooperation with system architects and integration teams.
 
Position Details
Location: Lund
Start date: As soon as possible
Duration: 12 months, extension possible
 
Competence/Experience – Mandatory
Experience from FPGA/ASIC Design/Verification (7+ years)
Excellent knowledge of RTL design in System Verilog
Experience from UVM methodology
Experience from IP level and system level verification
Proficient in verification planning, reporting and driving verification closure
Experience from UNIX and/or Linux
Excellent debugging skills with complex SoC designs
English (verbal and writing)



Competence/Experience – Optional
Experience with UART, SPI, I3C protocols
Experience with analog-mixed-signal type ASICs
Experience using formal properties and tools, such as Jasper, OneSpin, InFact and similar
Experience in using golden models/reference models in a test bench
Experience in agile ways of working
Experience from ClearCase or Git version control system
Experience from VHDL
Experience from C-programming
Experience from scripting in Perl, Python, Bash or C-shell
Competence within the field of telecommunication and radio technology
Experience from working with Agile development methodology
Academic degree
Swedish (verbal and writing)



Personality
Good communication skills
Structured
Strong feeling for producing high quality work
Ability to work independently
Ability to work in teams



Application
You can apply by sending your CV (in English or Swedish) to cv@paventia.se.
 
If you have questions, please contact Ola Svensson at +46 708 190 200 or ola.svensson@paventia.se.