Verification environment (creation / adaptation / maintenance).
Test case creation & execution
Most of the verification uses constrained random methodology but also dedicated test vectors and assertions are used. A successful candidate is an experienced design & verification engineer with 5+ years experience of design & verification (verification must be done using SystemVerilog / UVM).
Required skills and experiences:
Strong programming skills (VHDL, C).
Experienced in Hardware design / systemization.
Experience in system level verification.
Good knowledge in using the SystemVerilog / UVM tools and methodology.
Knowledge of verification methodology in general.
Knowledge about Formal verification is a plus.
Knowledge of High Level Synthesis using is a plus.
Scripting skills using eg Python, TCL and / or Perl are a plus.
Knowledge about Agile ways of working is a plus.