ASIC Verification Engineer

Arbetsbeskrivning

We are looking for a ASIC Verification Engineer.


Experience in following fields:


Gate level Simulation(GLS),
Low Power Verification,
Analog Mix Signal co-simulation (AMS Verification),
Jasper Connectivity Check (Formal Verification),
UVC development from scratch and SV assertion development.
Verification Spec development to Verification sign off with code and functional coverage closure.



Protocol Knowledge: AXI, CPRI, PCIE

Sammanfattning

  • Arbetsplats: Rediflex AB Malmö
  • 1 plats
  • 6 månader eller längre
  • Heltid
  • Fast månads- vecko- eller timlön
  • Publicerat: 5 augusti 2020
  • Ansök senast: 19 augusti 2020

Postadress

Ingenjörsgatan 22
Malmö, 21568

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