ASIC Verification Engineer

Job description:

You will be part of a high end technology project with the goal to develop and verify complex digital mobile communication designs where your responsibility will be either top or block level verification of an ASIC design.


Required competence (need to have)

Minimum 5 years experience of ASIC/FPGA verification
Documented previous SystemVerilog experience
UVM/OVM experience
Experience from verification of complex digital SoC designs with CPUs, DSPs, advanced filters and high speed links
Candidates must be good team players with attention to detail, self-disciplined, able to manage their own time and workload, proactive and motivated
Candidates shall also have good written and verbal communication skills in English


Wanted competence (nice to have)

Experience from C++, Specman (e), VHDL, Verilog, SystemC, PERL