ASIC verification SystemVerilog OVM or UVM

ASIC verification SystemVerilog OVM or UVM, Stockholm

We are looking for an ASIC verification engineer with SystemVerilog UVM (or OVM) experience to develop very large and complex ASIC's with high technical demands.

Job description

* The customer develops advanced telecom systems with high data rates. * You will working with among the most advanced and complex ASIC's in the world in 28 nm. * You will be working in a team of several ASIC developers.

Competence/Experience - Must have

* Experience of working with complex ASIC verification with several DSP's, CPU's and high speed links * 3 years experience of working with SystemVerilog UVM (pref) or OVM * Experience from block level verification, functional verification, test coverage strategies * Experience of design i VHDL * Fluent in English (verbal and writing)

Competence/Experience - Nice to have

* Experience of building test benches using OVC for SystemVerilog * Experience from formal verification, using assertions and constraints * Experience from top level verification * Experience of SystemC and TLM * Experience of Specman (e language, tools and methodology and building eVC's)

Personality

* Self-motivated and driven, take initiative, open, see big picture, like challenges * Social, team player

Assignment info

* Location: Stockholm onsite * Assignment duration: initially 6 months, with high possibility for extension