ASIC/FPGA Verification Engineer

You will be part of a high end technology project with the goal to develop and verify complex digital mobile communication designs
Your responsibility will be either top or block level verification of a ASIC/FPGA design


Required competence (need to have)

Minimum 5 years experience of ASIC/FPGA verification
Documented previous Specman (e) and/or SystemVerilog experience
Experience from verification of complex digital SoC designs with CPUs, DSPs, advanced filters and high speed links
Candidates must be good team players with attention to detail, self-disciplined, able to manage their own time and workload, proactive and motivated
Candidates shall also have good written and verbal communication skills in English


Wanted competence (nice to have)

Experience from C++, VHDL, Verilog, SystemC, PERL
Xilinx and/or Altera experience


Assignment start:
ASAP
Initially for 6 months but most likely extended