Implementing infrastructure

We are looking for a candidate for a 6-months assignment, implementing an infrastructure for ASIC-prototyping of signal-processing functions in Xilinx FPGAs.
 
Start date: February/March (The earlier the better)
 
Must-have:
-          Xilinx Vivado 2018 or later
-          Experience with Xilinx Virtex Ultrascale(+), if not then Xilinx 7-series would be OK.
-          VHDL
-          2-3 years professional experience working with FPGAs
-          Experience with floorplanning and timing-closure in Xilinx FPGAs
-          Strong communication skills
 
Good-to-have:
-          Fundamental understanding of Digital Signal Processing (filters, frequency transforms etc.)
-          Xilinx ILA /ChipScope
-          Xilinx HLS flow
-          Version management in ClearCase