OBS! Ansökningsperioden för denna annonsen har
passerat.
Arbetsbeskrivning
Expereince level :3 to 10 years.
Hands on in ASIC/FPGA level RTL Design
Hands on in Clock Domain Crossing (CDC) checks, Linting, equivalence checks
Experience in Digital module micro-architecture and design
Experience in basic RTL simulation
Good knowledge of Synthesis, STA and DFT aware design
Good knowledge of ARM subsystem, AMBA bus
Familiar with DSP subsystems and high speed interfaces (e.g. SERDES, GigE, 10GE)
Ability to lead & motivate a team of Engineer
Experience in Automotive industry would be plus with LIDAR protocol knowledge.