ASIC UVM Verifier

We are currently looking for 3 positions in to contribute in bringing bright ideas and complex designs to life.
We are seeking for skilled ASIC-verification engineers to be part of a successful team.
You will be involved in new and existing ASIC projects working in teams. The work can be carried out either at a modern and airy head office in Solna - Stockholm or at our clients customers offices in the Stockholm area.
The team is currently working on a mix of IP design/verification and different level of SubSys integration/verification.
Knowledge and experience:
• We are looking for a broad scale of experience, but preferable you should have been working with UVM for at least one year
• Good command of UVM verification and SystemVerilog
• Used to work with complex ASIC and/or large FPGA design
• Experience from IP block verification
• Multi clock domains
• RTL within Verilog, VHDL and/or SystemVerilog
• Good English skills, in both speech and writing
Meritorious if you have:
• Test bench structuring and design
• Leadership qualities
• RTL design knowledge
• Scripting skills
• Lab experience
•Telecommunication
ALL APPLICANTS MUST HAVE THE RIGHT TO WORK IN SWEDEN
PLEASE ENSURE YOU MEET THE ELIGIBILITY CRITERIA IN ORDER TO WORK IN SWEDEN.